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for the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the MAX108 pecl-compatible, 1.5gsps, 8-bit analog- to-digital converter (adc) allows accurate digitizing of analog signals with bandwidths to 2.2ghz. fabricated on maxims proprietary advanced gst-2 bipolar process, the MAX108 integrates a high-performance track/hold (t/h) amplifier and a quantizer on a single monolithic die. the innovative design of the internal t/h, which has an exceptionally wide 2.2ghz full-power input bandwidth, results in high performance (typically 7.5 effective bits) at the nyquist frequency. a fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance. unlike other adcs that can have errors resulting in false full- or zero-scale outputs, the MAX108 limits the error mag- nitude to 1lsb. the analog input is designed for either differential or single-ended use with a 250mv input voltage range. dual, differential, positive-referenced emitter-coupled logic (pecl)-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. the pecl outputs can be operated from any supply between +3v to +5v for compatibility with +3.3v or +5v referenced systems. control inputs are provided for interleaving additional MAX108 devices to increase the effective system sampling rate. the MAX108 is packaged in a 25mm x 25mm, 192-con- tact enhanced super ball-grid array (esbga?) and is specified over the commercial (0c to +70c) tempera- ture range. for pin-compatible, lower speed versions of the MAX108, see the max104 (1gsps) and the max106 (600msps) data sheets. applications digital rf/if signal processing direct rf downconversion high-speed data acquisition digital oscilloscopes high-energy physics radar/ecm systems ate systems features ? 1.5gsps conversion rate ? 2.2ghz full-power analog input bandwidth ? 7.5 effective bits at f in = 750mhz (nyquist frequency) ? 0.25lsb inl and dnl ? 50 differential analog inputs ? 250mv input signal range ? on-chip, +2.5v precision bandgap voltage reference ? latched, differential pecl digital outputs ? selectable 8:16 demultiplexer ? internal demux reset input with reset output ? 192-contact esbga package ? pin compatible with max104 (1gsps) and max106 (600msps) MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ________________________________________________________________ maxim integrated products 1 19-1492; rev 0; 9/99 part MAX108chc 0c to +70c temp. range pin-package 192 esbga evaluation kit available ordering information esbga top view MAX108 typical operating circuit appears at end of data sheet. 192-contact esbga ball assignment matrix esbga is a trademark of amkor/anam. pcb land pattern appears at end of data sheet.
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc a to gnda .........................................................-0.3v to +6v v cc d to gndd.........................................................-0.3v to +6v v cc i to gndi ............................................................-0.3v to +6v v cc o to gndd ........................................-0.3v to (v cc d + 0.3v) auxen1, auxen2 to gnd .....................-0.3v to (v cc d + 0.3v) v ee to gndi..............................................................-6v to +0.3v between gnds......................................................-0.3v to +0.3v v cc a to v cc d .......................................................-0.3v to +0.3v v cc a to v cc i.........................................................-0.3v to +0.3v pecl digital output current ...............................................50ma refin to gndr ........................................-0.3v to (v cc i + 0.3v) refout current ................................................+100a to -5ma iconst, iptat to gndi .......................................-0.3v to +1.0v ttl/cmos control inputs (demuxen, divselect) ......................-0.3v to (v cc d + 0.3v) rstin+, rstin- ......................................-0.3v to (v cc o + 0.3v) vosadj adjust input ................................-0.3v to (v cc i + 0.3v) clk+ to clk- voltage difference..........................................3v clk+, clk-.....................................(v ee - 0.3v) to (gndd + 1v) clkcom.........................................(v ee - 0.3v) to (gndd + 1v) vin+ to vin- voltage difference ............................................2v vin+, vin- to gndi................................................................2v continuous power dissipation (t a = +70c) 192-contact esbga (derate 61mw/c above +70c) ....4.88w (with heatsink and 200 lfm airflow, derate 106mw/c above +70c) .....................................8.48w operating temperature range MAX108chc.........................................................0c to +70c operating junction temperature.....................................+150c storage temperature range .............................-65c to +150c dc electrical characteristics (v cc a = v cc i = v cc d = +5.0v 5%, v ee = -5.0v 5%, v cc o = +3.0v to v cc d, refin connected to refout, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol min typ max units missing codes none codes differential nonlinearity (note 1) dnl -0.5 0.25 0.5 lsb full-scale input range v fsr 475 500 525 mvp-p common-mode input range v cm 0.8 v input resistance r in 49 50 51 input resistance temperature coefficient tc r 150 ppm/c resolution res 8 bits integral nonlinearity (note 1) inl -0.5 0.25 0.5 lsb input resistance (note 2) r vos 14 25 k input v os adjust range 4 5.5 lsb reference output voltage refout 2.475 2.50 2.525 v reference output load regulation ? refout 5 mv reference input resistance r ref 45 k conditions no missing codes guaranteed t a = +25c note 1 signal + offset w.r.t. gndi vosadj = 0 to 2.5v vin+ and vin- to gndi, t a = +25c driving refin input only 0 < i source < 2.5ma referenced to gndr t a = +25c accuracy analog inputs vos adjust control input reference input and output
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc a = v cc i = v cc d = +5.0v 5%, v ee = -5.0v 5%, v cc o = +3.0v to v cc d, refin connected to refout, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) pecl digital outputs (note 5) negative power-supply rejection ratio (note 8) psrr- 40 68 db (note 10) common-mode rejection ratio (note 7) cmrr 40 68 db positive power-supply rejection ratio (note 8) psrr+ 40 73 db vin+ = vin- = 0.1v (note 9) positive analog supply current i cc a 480 780 ma positive input supply current i cc i 108 150 ma negative input supply current i ee -290 -210 ma digital supply current i cc d 205 340 ma output supply current (note 6) i cc o 75 115 ma power dissipation (note 6) p diss 5.25 w digital output high voltage v oh -1.025 -0.880 v digital output low voltage v ol -1.810 -1.620 v parameter symbol min typ max units high-level input voltage v ih 2.0 v low-level input voltage v il 0.8 v high-level input current i ih 50 a clock input resistance r clk 48 50 52 input resistance temperature coefficient tc r 150 ppm/c low-level input current i il -1 1 a digital input high voltage v ih -1.165 v digital input low voltage v il -1.475 v conditions v il = 0 v ih = 2.4v clk+ and clk- to clkcom, t a = +25c clock inputs (note 3) ttl/cmos control inputs (demuxen, divselect) demux reset input (note 4) power requirements pecl digital outputs (note 5)
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 4 _______________________________________________________________________________________ ac electrical characteristics (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 1.5gsps, f in at -1dbfs, t a = +25c, unless otherwise noted.) transfer curve offset v os -2.0 0 +2.0 lsb vosadj control input open single-ended differential 45.7 48.2 signal-to-noise ratio and distortion (note 11) sinad 250 48.2 db f in = 250mhz single-ended differential 44.5 47.0 single-ended differential sinad 750 47.1 44.3 sinad 1500 44.4 f in = 1500mhz f in = 750mhz single-ended differential 55.0 61.6 spurious-free dynamic range sfdr 250 61.7 db f in = 250mhz single-ended differential 50.0 54.0 single-ended differential sfdr 750 54.1 44.6 sfdr 1500 45.5 f in = 1500mhz f in = 750mhz single-ended differential -55.5 -60.2 total harmonic distortion (note 12) thd 250 -61.3 db f in = 250mhz single-ended differential -49.0 -52.1 single-ended differential thd 750 -52.8 -44.5 thd 1500 -44.2 f in = 1500mhz f in = 750mhz single-ended differential 44.2 47.4 signal-to-noise ratio (no harmonics) snr 250 47.4 db f in = 250mhz single-ended differential 43.3 46.8 snr 750 46.9 f in = 750mhz single-ended differential 7.3 7.71 effective number of bits (note 11) enob 250 7.71 bits single-ended differential f in = 250mhz 44.8 snr 1500 44.9 f in = 1500mhz single-ended differential 7.1 7.51 enob 750 7.53 f in = 750mhz single-ended differential parameter symbol min typ max units 7.07 analog input vswr vswr 1.1:1 v/v analog input full-power bandwidth bw -3db 2.2 ghz enob 1500 7.07 two-tone intermodulation imd -66.8 db conditions f in = 1500mhz f in = 500mhz f in1 = 247mhz, f in2 = 253mhz, at -7db below full-scale analog input dynamic specifications
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier _______________________________________________________________________________________ 5 ac electrical characteristics (continued) (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 1.5gsps, f in at -1dbfs, t a = +25c, unless otherwise noted.) div4 mode div1, div2 modes 7.5 div4 mode div1, div2 modes figures 6, 7, 8 t pdp auxiliary port pipeline delay t pda 9.5 clock cycles figures 6, 7, 8 8.5 dready to data propagation delay (note 14) t pd2 -50 150 350 ps figure 17 clk to dready propagation delay t pd1 2.2 ns figure 17 reset input data hold time (note 13) t hd 0 ps figure 15 clock pulse width high t pwh 0.3 5 ns figure 17 parameter symbol min typ max units aperture jitter t aj <0.5 ps aperture delay t ad 100 ps reset input data setup time (note 13) t su 0 ps data rise time t rdata 420 ps maximum sample rate f max 1.5 gsps clock pulse width low t pwl 0.3 ns data fall time t fdata 360 ps dready rise time t rdready 220 ps dready fall time t fdready 180 ps primary port pipeline delay 7.5 clock cycles conditions figure 4 figure 4 figure 15 20% to 80%, c l = 3pf 20% to 80%, c l = 3pf 20% to 80%, c l = 3pf 20% to 80%, c l = 3pf figure 17 timing characteristics note 1: static linearity parameters are computed from a best-fit straight line through the code transition points. the full-scale range (fsr) is defined as 256 times the slope of the line. note 2: the offset control input is a self-biased voltage divider from the internal +2.5v reference voltage. the nominal open-circuit voltage is +1.25v. it may be driven from an external potentiometer connected between refout and gndi. note 3: the clock inputs termination voltage can be operated between -2.0v and gndi. observe the absolute maximum ratings on the clk+ and clk- inputs. note 4: input logic levels are measured with respect to the v cc o power-supply voltage. note 5: all pecl digital outputs are loaded with 50 to v cc o - 2.0v. measurements are made with respect to the v cc o power- supply voltage. note 6: the current in the v cc o power supply does not include the current in the digital outputs emitter followers, which is a func- tion of the load resistance and the v tt termination voltage. note 7: common-mode rejection ratio (cmrr) is defined as the ratio of the change in the transfer-curve offset voltage to the change in the common-mode voltage, expressed in db. note 8: power-supply rejection ratio (psrr) is defined as the ratio of the change in the transfer-curve offset voltage to the change in power-supply voltage, expressed in db. note 9: measured with the positive supplies tied to the same potential; v cc a = v cc d = v cc i. v cc varies from +4.75v to +5.25v. note 10: v ee varies from -5.25v to -4.75v.
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 6 _______________________________________________________________________________________ note 11: effective number of bits (enob) and signal-to-noise plus distortion (sinad) are computed from a curve fit referenced to the theoretical full-scale range. note 12: total harmonic distortion (thd) is computed from the first five harmonics. note 13: guaranteed by design with a reset pulse width one clock period long or greater. note 14: guaranteed by design. the dready to data propagation delay is measured from the 50% point on the rising edge of the dready signal (when the output data changes) to the 50% point on a data output bit. this places the falling edge of the dready signal in the middle of the data output valid window, within the differences between the dready and data rise and fall times, which gives maximum setup and hold time for latching external data latches. typical operating characteristics (v cc a = v cc i = v cc d = +5v, v ee = -5v, v cc o = +3.3v, refin connected to refout, f s = 1.5gsps, t a = +25c, unless otherwise noted.) 6.25 100 2000 1000 effective number of bits vs. analog input frequency (single-ended analog input drive) 6.75 6.50 7.00 7.25 7.50 7.75 8.00 MAX108 toc01 analog input frequency (mhz) enob (bits) 10 -1dbfs -12dbfs -6dbfs 6.25 100 2000 1000 effective number of bits vs. analog input frequency (differential analog input drive) 6.75 6.50 7.00 7.25 7.50 7.75 8.00 MAX108 toc02 analog input frequency (mhz) enob (bits) 10 -1dbfs -12dbfs -6dbfs 40 100 2000 1000 signal-to-noise plus distortion vs. analog input frequency (single-ended analog input drive) 42 41 43 44 45 46 47 48 49 50 MAX108 toc03 analog input frequency (mhz) sinad (db) 10 -6dbfs -1dbfs -12dbfs 40 100 2000 1000 signal-to-noise plus distortion vs. analog input frequency (differential analog input drive) 42 41 43 44 45 46 47 48 49 50 MAX108 toc04 analog input frequency (mhz) sinad (db) 10 -1dbfs -12dbfs -6dbfs 30 100 2000 1000 signal-to-noise ratio vs. analog input frequency (single-ended analog input drive) 42 38 34 46 50 MAX108 toc05 analog input frequency (mhz) snr (db) 10 -1dbfs -12dbfs -6dbfs 30 100 2000 1000 signal-to-noise ratio vs. analog input frequency (differential analog input drive) 42 38 34 46 50 MAX108 toc06 analog input frequency (mhz) snr (db) 10 -1dbfs -12dbfs -6dbfs
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier _______________________________________________________________________________________ 7 35 100 2000 1000 spurious-free dynamic range vs. analog input frequency (single-ended analog input drive) 55 50 60 45 40 65 70 MAX108 toc07 analog input frequency (mhz) sfdr (db) 10 -1dbfs -12dbfs -6dbfs 35 100 2000 1000 spurious-free dynamic range vs. analog input frequency (differential analog input drive) 55 50 60 45 40 65 70 MAX108 toc08 analog input frequency (mhz) sfdr (db) 10 -1dbfs -12dbfs -6dbfs 100 1000 1500 effective number of bits vs. clock frequency (f in = 250mhz, 1dbfs) MAX108 toc09 clock frequency (mhz ) enob (bits) 8.00 6.50 6.75 7.00 7.25 7.50 7.75 8.00 6.50 -12 -10 -6 -2 2 6 -8 -4 0 4 10 8 effective number of bits vs. clock power (f in = 250mhz, -1dbfs) 6.75 7.00 7.25 7.50 7.75 MAX108toc10 clock power (dbm) per side enob (bits) single-ended clock drive differential clock drive 47 51 49 57 55 53 59 61 65 63 67 -12 -10 -8 -6 -4 -2 0 2 4 8 610 spurious-free dynamic range vs. clock power (f in = 250mhz, -1dbfs) MAX108toc13 clock power (dbm) per side sfdr (db) differential clock drive single-ended clock drive 6.50 7.25 7.00 6.75 7.50 7.75 8.00 4.5 4.9 4.7 5.1 5.3 5.5 effective number of bits vs. v cc i = v cc a = v cc d (f in = 250mhz, -1dbfs) MAX108-11 v cc (v) enob (bits) 6.50 7.25 7.00 6.75 7.50 7.75 8.00 -5.5 -5.1 -5.3 -4.9 -4.7 -4.5 effective number of bits vs. v ee (f in = 250mhz, -1dbfs) MAX108-12 v ee (v) enob (bits) 57 59 58 61 60 63 62 64 66 65 67 4.5 4.7 4.9 5.1 5.3 5.5 spurious-free dynamic range vs. v cc i = v cc a = v cc d (f in = 250mhz, -1dbfs) MAX108-14 v cc (v) sfdr (db) 57 59 58 61 60 63 62 64 66 65 67 -5.5 -5.3 -5.1 -4.9 -4.7 -4.5 spurious-free dynamic range vs. v ee (f in = 250mhz, -1dbfs) MAX108-15 v ee (v) sfdr (db) typical operating characteristics (continued) (v cc a = v cc i = v cc d = +5v, v ee = -5v, v cc o = +3.3v, refin connected to refout, f s = 1.5gsps, t a = +25c, unless otherwise noted.)
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v cc a = v cc i = v cc d = +5v, v ee = -5v, v cc o = +3.3v, refin connected to refout, f s = 1.5gsps, t a = +25c, unless otherwise noted.) -64 -62 -63 -60 -61 -58 -59 -57 -55 -56 -54 4.5 4.7 4.9 5.1 5.3 5.5 total harmonic distortion vs. v cc i = v cc a = v cc d (f in = 250mhz, -1dbfs) MAX108-16 v cc (v) thd (db) -64 -62 -63 -60 -61 -58 -59 -57 -55 -56 -54 -5.5 -5.3 -5.1 -4.9 -4.7 -4.5 total harmonic distortion vs. v ee (f in = 250mhz, -1dbfs) MAX108-17 v ee (v) thd (db) -128.0 -102.4 -51.2 -76.8 -25.6 0 0 300 150 450 600 750 fft plot (f in = 250.9460449mhz, record length 16,384) MAX108 toc18 analog input frequency (mhz) amplitude (db) enob = 7.73 sinad = 48.3db snr = 47.3db thd = -59.9db sfdr = 61.5db h3 h2 fundamental -128.0 -102.4 -51.2 -76.8 -25.6 0 0 300 150 450 600 750 fft plot (f in = 747.1618562mhz, record length 16,384) MAX108 toc19 analog input frequency (mhz) amplitude (db) enob = 7.61 sinad = 47.6db snr = 46.7db thd = -56.5db sfdr = 59.4db h3 h2 fundamental -5 -6 -7 -8 -9 -10 500 1500 2500 analog input bandwidth -6db below full scale MAX108toc22 analog input frequency (mhz) amplitude (db) small-signal bandwidth = 2.4ghz -128.0 -102.4 -51.2 -76.8 -25.6 0 0 300 150 450 600 750 fft plot (f in = 1503.021240mhz, -1dbfs, record length 16,384) MAX108 toc20 analog input frequency (mhz) amplitude (db) enob = 7.12 sinad = 44.6db snr = 44.7db thd = -44.4db sfdr = 44.4db h3 h2 fundamental -128.0 -102.4 -51.2 -76.8 -25.6 0 0 300 150 450 600 750 fft plot (f in = 1503.021240mhz, -3dbfs, record length 16,384) MAX108 toc21 analog input frequency (mhz) amplitude (db) enob = 7.60 sinad = 47.5db snr = 42.0db thd = -51.3db sfdr = 51.3db h3 h2 fundamental 0 -1 -2 -3 -4 -5 500 1500 2500 analog input bandwidth full power MAX108toc23 analog input frequency (mhz) amplitude (db) full-power bandwidth = 2.2ghz -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 integral nonlinearity vs. output code (low-frequency servo-loop data) MAX108toc24 output code inl (lsb)
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v cc a = v cc i = v cc d = +5v, v ee = -5v, v cc o = +3.3v, refin connected to refout, f s = 1.5gsps, t a = +25c, unless otherwise noted.) -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 differential nonlinearity vs. output code (low-frequency servo-loop data) MAX108toc25 output code dnl (lsb) dready 200mv/div data 200mv/div dready rise/fall time, data-output rise/fall time MAX108 toc26 500ps/div 1.0 1.1 1.2 1.3 1.4 1.5 0 1000 500 1500 2000 2500 vswr vs. analog input frequency MAX108toc27 analog input frequency (mhz) vswr -128.0 -102.4 -51.2 -76.8 -25.6 0 0 300 150 450 600 750 two-tone intermodulation fft plot (f in1 = 247.1008301mhz, f in2 = 253.3264160mhz, 7db below full scale, record length 16,384) MAX108 toc28 analog input frequency (mhz) amplitude (db) f in 1 f in 2 pin description name function a1Ca4, a6, a7, b1, b2, c1, c2, d1Cd3, g1, h1, j2, j3, k1Ck3, l2, l3, m1, n1, t2, t3, u1, v1, v2, w1Cw4 gndi analog ground. for t/h amplifier, clock distribution, bandgap reference, and reference amplifier. a5, b5, c5, h2, h3, m2, m3, u5, v5, w5 v cc i analog supply voltage, +5v. supplies t/h amplifier, clock distri- bution, bandgap reference, and reference amplifier. contact a8, b8, c8, u6, v6, w6 gnda analog ground. for comparator array. a9, b9, c9, u7, v7, w7 v cc a analog supply voltage, +5v. supplies analog comparator array. a11, b11, b16, b17, c11, c16, u9, u17, v9, v17, v18, w9 gndd digital ground a10, e17, f2, p3, r17, r18 testpoint (t.p.) test point. do not connect.
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 10 ______________________________________________________________________________________ pin description (continued) h18 p3+ primary output data bit 3 h17 p3- complementary primary output data bit 3 f17 p2- complementary primary output data bit 2 g17 a2- complementary auxiliary output data bit 2 g18 a2+ auxiliary output data bit 2 f18 p2+ primary output data bit 2 e18 demuxen ttl/cmos demux enable control 1: enable demux 0: disable demux f1 vosadj offset adjust input e2 iptat die temperature measurement test point. see die temperature measurement section. c7 refout reference output c15 a1- complementary auxiliary output data bit 1 d18 auxen2 connect to v cc o to power the auxiliary port, or connect to gndd to power down. e1 iconst die temperature measurement test point. see die temperature measurement section. d17 divselect ttl/cmos demux divide selection input 1: decimation div4 mode 0: demultiplexed div2 mode c13 a0- complementary auxiliary output data bit 0 (lsb) c14 p1- complementary primary output data bit 1 c12 p0- complementary primary output data bit 0 (lsb) b13 a0+ auxiliary output data bit 0 (lsb) b15 a1+ auxiliary output data bit 1 c6 refin reference input b14 p1+ primary output data bit 1 b10, b18, c10, c17, c18, t17, t18, u8, u18, v8, w8 v cc d digital supply voltage, +5v b12 p0+ primary output data bit 0 (lsb) b6, b7 gndr reference ground. must be connected to gndi. name function a12Ca19, b19, c19, d19, e19, f19, g19, h19, j19, k19, l19, m19, n19, p19, t19, u19, v19, w10Cw19 v cc o pecl supply voltage, +3v to +5v contact b3, b4, c3, c4, e3, f3, g2, g3, n2, n3, u2Cu4, v3, v4 v ee analog supply voltage, -5v. supplies t/h amplifier, clock distribu- tion, bandgap reference, and reference amplifier.
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 11 pin description (continued) k18 dready+ data-ready clock l1 vin+ differential input voltage (+) k17 dready- complementary data-ready clock v13 a7+ auxiliary output data bit 7 (msb) v15 a6+ auxiliary output data bit 6 v16 p6+ primary output data bit 6 v14 p7+ primary output data bit 7 (msb) v12 or+ pecl overrange bit v10 rstin+ pecl demux reset input v11 rstout+ pecl reset output u13 a7- complementary auxiliary output data bit 7 (msb) u15 a6- complementary auxiliary output data bit 6 u16 p6- complementary primary output data bit 6 u14 p7- complementary primary output data bit 7 (msb) u12 or- complementary pecl overrange bit r19 auxen1 connect to v cc o to power the auxiliary port, or connect to gndd to power down. u10 rstin- complementary pecl demux reset input u11 rstout- complementary pecl reset output t1 clk+ sampling clock input r1Cr3 clkcom 50 clock termination return p18 a5+ auxiliary output data bit 5 m17 a4- complementary auxiliary output data bit 4 p1 clk- complementary sampling clock input p2 testpoint (t.p.) this contact must be connected to gndi. name function p17 a5- complementary auxiliary output data bit 5 contact n17 p5- complementary primary output data bit 5 n18 p5+ primary output data bit 5 m18 a4+ auxiliary output data bit 4 j17 a3- complementary auxiliary output data bit 3 l17 p4- complementary primary output data bit 4 l18 p4+ primary output data bit 4 j18 a3+ auxiliary output data bit 3 j1 vin- differential input voltage (-)
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 12 ______________________________________________________________________________________ _______________detailed description the MAX108 is an 8-bit, 1.5gsps flash analog-to-digital converter (adc) with on-chip t/h amplifier and differ- ential pecl-compatible outputs. the adc (figure 1) employs a fully differential 8-bit quantizer and a unique encoding scheme to limit metastable states, with no error exceeding 1lsb max. an integrated 8:16 output demultiplexer simplifies inter- facing to the part by reducing the output data rate to one-half the sampling clock rate. this demultiplexer has internal reset capability that allows multiple MAX108s to be time-interleaved to achieve higher effective sampling rates. when clocked at 1.5gsps, the MAX108 provides a typi- cal enob of 7.5 bits at an analog input frequency of 750mhz. the analog input of the MAX108 is designed for differential or single-ended use with a 250mv full- scale input range. in addition, this fast adc features an on-chip +2.5v precision bandgap reference. if desired, an external reference can also be used. figure 1. simplified functional diagram clk- rstin+ rstin- vosadj bandgap reference +2.5v clk+ clkcom vin- vin+ ref out ref in demuxen divselect demux clock driver 16 50 w 50 w 50 w 50 w rstout a0?7 p0?7 dready or differential pecl outputs t/h clock driver adc clock driver reference amplifier 2 2 demux clock generator reset input dual latch reset pipeline gndi gndi gndr delayed reset 16 16 2 2 t/h amplifier logic clock driver bias currents overrange bit auxiliary data port primary data port data ready clock demux reset output 8-bit flash adc MAX108
principle of operation the MAX108s flash or parallel architecture provides the fastest multibit conversion of all common integrated adc designs. the key to this high-speed flash archi- tecture is the use of an innovative, high-performance comparator design. the flash converter and down- stream logic translate the comparator outputs into a parallel 8-bit output code and pass this binary code on to the optional 8:16 demultiplexer, where primary and auxiliary ports output pecl-compatible data at up to 750msps per port (depending on how the demultiplex- er section is set on the MAX108). the ideal transfer function appears in figure 2. on-chip track/hold amplifier as with all adcs, if the input waveform is changing rapidly during conversion, enob and signal-to-noise ratio (snr) specifications will degrade. the MAX108s on-chip, wide-bandwidth (2.2ghz) t/h amplifier reduces this effect and increases the enob perfor- mance significantly, allowing precise capture of fast analog data at high conversion rates. the t/h amplifier buffers the input signal and allows a full-scale signal input range of 250mv. the t/h ampli- fiers differential 50 input termination simplifies inter- facing to the MAX108 with controlled impedance lines. figure 3 shows a simplified diagram of the t/h amplifier stage internal to the MAX108. aperture width, delay, and jitter (or uncertainty) are parameters that affect the dynamic performance of high-speed converters. aperture jitter, in particular, directly influences snr and limits the maximum slew rate (dv/dt) that can be digitized without contributing significant errors. the MAX108s innovative t/h amplifier design limits aperture jitter typically to less than 0.5ps. aperture width aperture width (t aw ) is the time the t/h circuit requires (figure 4) to disconnect the hold capacitor from the input circuit (for instance, to turn off the sampling bridge and put the t/h unit in hold mode). aperture jitter aperture jitter (t aj ) is the sample-to-sample variation (figure 4) in the time between the samples. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 4). internal reference the MAX108 features an on-chip +2.5v precision bandgap reference that can be used by connecting MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 13 (-fs + 1lsb) 0 +fs (+fs - 1lsb) 255 255 254 129 128 127 126 3 2 1 0 analog input overrange + digital output figure 2. transfer function to comparators to comparators buffer amplifier input amplifier clock splitter all inputs are esd protected (not shown in this simplified drawing). sampling bridge gndi 50 w 50 w vin+ vin- gndi c hold 50 w 50 w clk+ clk- clkcom figure 3. internal structure of the 2.2ghz t/h amplifier hold clk analog input sampled data (t/h) t/h t aw t ad t aj track track aperture delay (t ad ) aperture width (t aw ) aperture jitter (t aj ) clk figure 4. t/h aperture timing
MAX108 refout to refin. this connects the reference output to the positive input of the reference buffer. the buffers negative input is internally connected to gndr. gndr must be connected to gndi on the users application board. if required, refout can source up to 2.5ma to supply external devices. an adjustable external reference can be used to adjust the adcs full-scale range. to use an external refer- ence supply, connect a high-precision reference to the refin pin and leave the refout pin floating. in this configuration, refout must not be simultaneously connected, to avoid conflicts between the two refer- ences. refin has a typical input resistance of 5k and accepts input voltages of +2.5v 200mv. for best per- formance, maxim recommends using the MAX108s internal reference. digital outputs the MAX108 provides data in offset binary format to differential pecl outputs. a simplified circuit schematic of the pecl output cell is shown in figure 5. all pecl outputs are powered from v cc o, which may be operat- ed from any voltage between +3.0v to v cc d for flexible interfacing with either +3.3v or +5v systems. the nomi- nal v cc o supply voltage is +3.3v. all pecl outputs on the MAX108 are open-emitter types and must be terminated at the far end of each transmission line with 50 to v cc o - 2v. table 1 lists all MAX108 pecl outputs and their functions. demultiplexer operation the MAX108 features an internal demultiplexer that provides for three different modes of operation (see the following sections on demultiplexed div2 mode, non- demultiplexed div1 mode, and decimation div4 mode ) controlled by two ttl/cmos-compatible inputs: demuxen and divselect. demuxen enables or disables operation of the internal 1:2 demultiplexer. a logic high on demuxen activates the internal demultiplexer, and a logic low deactivates it. with the internal demultiplexer enabled, divselect controls the selection of the operational mode. divse- lect low selects demultiplexed div2 mode, and div- select high selects decimation div4 mode (table 2). 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 14 ______________________________________________________________________________________ diff. pair 500 w 500 w 1.8ma gndd gndd gndd v cc o a_+/p_+ a_-/p_- figure 5. simplified pecl output structure table 1. pecl output functions functional description p0+ to p7+, p0- to p7- primary-port differential outputs from lsb to msb. a + indicates the true outputs; a - denotes the complementary outputs. pecl output signals rstout+, rstout- reset output true and complementary outputs dready+, dready- data-ready clock true and complementary outputs. these signal lines are used to latch the output data from the primary to the auxiliary output ports. data changes on the rising edge of the dready clock. or+, or- overrange true and complementary outputs a0+ to a7+, a0- to a7- auxiliary-port differential outputs from lsb to msb. a + indicates the true outputs; a - denotes the complementary outputs.
non-demultiplexed div1 mode the MAX108 may be operated at up to 750msps in non-demultiplexed div1 mode (table 2). in this mode, the internal demultiplexer is disabled and sampled data is presented to the primary port only, with the data repeated at the auxiliary port but delayed by one clock cycle (figure 6). since the auxiliary output port contains the same data stream as the primary output port, the auxiliary port can be shut down to save power by connecting auxen1 and auxen2 to digital ground (gndd). this powers down the internal bias cells and causes both outputs (true and complemen- tary) of the auxiliary port to pull up to a logic-high level. to save additional power, the external 50 ter- mination resistors connected to the pecl termination power supply (v cc o - 2v) may be removed from all auxiliary output ports. demultiplexed div2 mode the MAX108 features an internally selectable div2 mode (table 2) that reduces the output data rate to one-half of the sample clock rate. the demultiplexed outputs are presented in dual 8-bit format with two con- secutive samples appearing in the primary and auxil- iary output ports on the rising edge of the data-ready clock (figure 7). the auxiliary data port contains the previous sample, and the primary output contains the most recent data sample. auxen1 and auxen2 must be connected to v cc o to power up the auxiliary port pecl output drives. MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 15 note: the auxiliary port data is delayed one additional clock cycle from the primary port data. grounding auxen1 and auxen2 will power down the auxiliary port to save power. clk- clk+ n n+1 n+2 n+3 n+4 n+5 n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready auxiliary data port primary data port dready+ dready- figure 6. non-demuxed, div1-mode timing diagram note: the latency to the primary port is 7.5 clock cycles, and the latency to the auxiliary port is 8.5 clock cycles. both the primary and auxiliary data ports are updated on the rising edge of the dready+ clock. clk- clk+ n n+1 n+2 n+3 n+4 n+5 n+1 n-1 n+3 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready auxiliary data port primary data port dready+ dready- n n+2 n+4 figure 7. demuxed div2-mode timing diagram
MAX108 decimation div4 mode the MAX108 also offers a special decimated, demulti- plexed output (figure 8) that discards every other input sample and outputs data at one-quarter the input sam- pling rate for system debugging at slower output data rates. with an input clock of 1.5ghz, the effective output data rate will be reduced to 375mhz per output port in the div4 mode (table 2). since every other sample is discarded, the effective sampling rate is 750msps. overrange operation a single differential pecl overrange output bit (or+, or-) is provided for both primary and auxiliary demulti- plexed outputs. the operation of the overrange bit depends on the status of the internal demultiplexer. in demultiplexed div2 mode and decimation div4 mode, the or bit will flag an overrange condition if either the primary or auxiliary port contains an overranged sam- ple (table 2). in non-demultiplexed div1 mode, the or port will flag an overrange condition only when the pri- mary output port contains an overranged sample. applications information single-ended analog inputs the MAX108 t/h amplifier is designed to work at full speed for both single-ended and differential analog inputs (figure 9). inputs vin+ and vin- feature on-chip, laser-trimmed 50 termination resistors to provide excellent voltage standing-wave ratio (vswr) perfor- mance. 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 16 ______________________________________________________________________________________ table 2. demultiplexer operation note: the latency to the primary port remains 7.5 clock cycles, while the latency of the auxiliary port increases to 9.5 clock cycl es. this effectively discards every other sample and reduces the output data rate to 1/4 the sample clock rate. clk- clk+ n n+1 n+2 n+3 n+4 n+5 n-2 n+2 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready auxiliary data port primary data port dready+ dready- n n+4 figure 8. decimation div4-mode timing diagram x = dont care div4 375msps/port high flags overrange data appearing in either the primary or auxiliary port. high demux mode div2 750msps/port div1 750msps (max) divselect low x overrange bit operation demuxen high low flags overrange data appearing in primary port only.
in a typical single-ended configuration, the analog input signal (figure 10a) enters the t/h amplifier stage at the in-phase input (vin+), while the inverted phase input (vin-) is reverse-terminated to gndi with an external 50 resistor. single-ended operation allows for an input amplitude of 250mv. table 3 shows a selec- tion of input voltages and their corresponding output codes for single-ended operation. differential analog inputs to obtain a full-scale digital output with differential input drive (figure 10b), 250mvp-p must be applied between vin+ and vin- (vin+ = +125mv, and vin- = -125mv). midscale digital output codes (01111111 or 10000000) occur when there is no voltage difference between vin+ and vin-. for a zero-scale digital output code, the in-phase (vin+) input must see -125mv and the invert- ed input (vin-) must see +125mv. a differential input drive is recommended for best performance. table 4 represents a selection of differential input voltages and their corresponding output codes. MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 17 +2.8v 50 w 50 w vin+ analog inputs are esd protected (not shown in this simplified drawing). vin- gndi v ee figure 9. simplified analog input structure (single-ended/ differential) v in+ v in- 0v +250mv -250mv t 500mvp-p fs analog input range v in = 250mv 500mv figure 10a. single-ended analog input signals v in+ v in- +125mv -125mv t 250mv fs analog input range 0v 250mv -250mv figure 10b. differential analog input signals table 3. ideal input voltage and output code results for single-ended operation 0 -250mv 00000000 (zero scale) 0v 0 -250mv + 1lsb 0000001 0 0v 01111111 toggles 10000000 0v 0v 0 +250mv - 1lsb 11111111 0v output code vin+ overrange bit 1 vin- +250mv 11111111 (full scale) 0v
MAX108 offset adjust the MAX108 provides a control input (vosadj) to com- pensate for system offsets. the offset adjust input is a self-biased voltage divider from the internal +2.5v preci- sion reference. the nominal open-circuit voltage is one- half the reference voltage. with an input resistance of typically 25k , this pin may be driven by an external 10k potentiometer (figure 11) connected between refout and gndi to correct for offset errors. this con- trol provides a typical 5.5lsb offset adjustment range. clock operation the MAX108 clock inputs are designed for either sin- gle-ended or differential operation (figure 12) with flexi- ble input drive requirements. each clock input is terminated with an on-chip, laser-trimmed 50 resistor to clkcom (clock-termination return). the clkcom termination voltage can be connected anywhere between ground and -2v for compatibility with standard ecl drive levels. the clock inputs are internally buffered with a preampli- fier to ensure proper operation of the data converter, even with small-amplitude sine-wave sources. the MAX108 was designed for single-ended, low-phase- noise sine-wave clock signals with as little as 100mv amplitude (-10dbm). this eliminates the need for an external ecl clock buffer and its added jitter. single-ended clock inputs (sine-wave drive) excellent performance is obtained by ac- or dc-cou- pling a low-phase-noise sine-wave source into a single clock input (figure 13a, table 5). for proper dc bal- ance, the undriven clock input should be externally 50 reverse-terminated to gndi. the dynamic performance of the data converter is essentially unaffected by clock-drive power levels from -10dbm (100mv clock signal amplitude) to +10dbm (1v clock signal amplitude). the MAX108 dynamic per- 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 18 ______________________________________________________________________________________ table 4. ideal input voltage and output code results for differential operation output code vin+ 0 -125mv 00000000 (zero scale) +125mv 0 -125mv + 0.5lsb 00000001 0 0v 01111111 toggles 10000000 +125mv - 0.5lsb 0v overrange bit 0 +125mv - 0.5lsb 11111111 1 vin- +125mv 11111111 (full scale) -125mv + 0.5lsb -125mv gndi pot 10k refout vosadj MAX108 figure 11. offset adjust with external 10k potentiometer clk+ clkcom clock inputs are esd protected (not shown in this simplified drawing). clk- 50 w +0.8v 50 w gndi v ee figure 12. simplified clock input structure (single-ended/ differential)
formance specifications are determined by a single- ended clock drive of +4dbm (500mv clock signal amplitude). to avoid saturation of the input amplifier stage, limit the clock power level to a maximum of +10dbm. differential clock inputs (sine-wave drive) the advantages of differential clock drive (figure 13b, table 5) can be obtained by using an appropriate balun or transformer to convert single-ended sine-wave sources into differential drives. the precision on-chip, laser-trimmed 50 clock-termination resistors ensure excellent amplitude matching. see single-ended clock inputs (sine-wave drive) for proper input amplitude requirements. single-ended clock inputs (ecl drive) configure the MAX108 for single-ended ecl clock drive by connecting the clock inputs as shown in figure 13c (table 5). a well-bypassed v bb supply (-1.3v) is essential to avoid coupling noise into the undriven clock input, which would degrade dynamic perfor- mance. differential clock inputs (ecl drive) drive the MAX108 from a standard differential (figure 13d, table 5) ecl clock source by setting the clock ter- mination voltage at clkcom to -2v. bypass the clock- termination return (clkcom) as close to the adc as possible with a 0.01f capacitor connected to gndi. MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 19 clk+ clk- = 0v +0.5v -0.5v note: clkcom = 0v t figure 13a. single-ended clock input signals clk+ clk- +0.5v -0.5v t note: clkcom = 0v figure 13b. differential clock input signals clk+ -0.8v -1.8v t clk- = -1.3v note: clkcom = -2v figure 13c. single-ended ecl clock drive clk+ clk- -0.8v -1.8v t note: clkcom = -2v figure 13d. differential ecl clock drive
MAX108 ac-coupling clock inputs the clock inputs clk+ and clk- can be driven with pecl logic if the clock inputs are ac-coupled. under this condition, connect clkcom to gndi. single- ended ecl/pecl/sine-wave drive is also possible if the undriven clock input is reverse-terminated to gndi through a 50 resistor in series with a capacitor whose value is identical to that used to couple the driven input. demux reset operation the MAX108 features an internal 1:2 demultiplexer that reduces the data rate of the output digital data to one- half the sample clock rate. demux reset is necessary when interleaving multiple MAX108s and/or synchroniz- ing external demultiplexers. the simplified block dia- gram of figure 1 shows that the demux reset signal path consists of four main circuit blocks. from input to out- put, they are the reset input dual latch, the reset pipeline, the demux clock generator, and the reset out- put. the signals associated with the demux reset opera- tion and the control of this section are listed in table 6. reset input dual latch the reset input dual-latch circuit block accepts differ- ential pecl reset inputs referenced to the same v cc o power supply that powers the MAX108 pecl outputs. for applications that do not require a synchronizing reset, the reset inputs can be left open. in this case, they will self-bias to a proper level with internal 50k resistors and 20a current source. this combination creates a -1v difference between rstin+ and rstin- to disable the internal reset circuitry. when driven with pecl logic levels terminated with 50 to (v cc o - 2v), the internal biasing network can easily be overdriven. figure 14 shows a simplified schematic of the reset input structure. to properly latch the reset input data, the setup time (t su ) and the data-hold time (t hd ) must be met with respect to the rising edge of the sample clock. the tim- ing diagram of figure 15 shows the timing relationship of the reset input and sampling clock. 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 20 ______________________________________________________________________________________ table 5. dc-coupled clock drive options -2v differential ecl figure 13d ecl drive ecl drive -2v single-ended ecl figure 13c -1.3v ecl drive gndi differential sine wave figure 13b -10dbm to +4dbm -10dbm to +4dbm clk- external 50 to gndi reference clock drive clkcom gndi clk+ single-ended sine wave figure 13a -10dbm to +4dbm 50k 50k rstin+ rstin- reset inputs are esd protected (not shown in this simplified drawing). 20 m a gndd v cc o figure 14. simplified reset input structure rstin+ 50% 50% clk+ clk- rstin- 50% t su t hd figure 15. reset input timing definitions
reset pipeline the next section in the reset signal path is the reset pipeline. this block adds clock cycles of latency to the reset signal to match the latency of the converted ana- log data through the adc. in this way, when reset data arrives at the rstout+/rstout- pecl output it will be time-aligned with the analog data present in the prima- ry and auxiliary ports at the time the reset input was deasserted at rstin+/rstin-. demux clock generator the demux clock generator creates the div1, div2, or div4 clocks required for the different modes of demux and non-demultiplexed operation. the ttl/cmos con- trol inputs demuxen and divselect control the demuxed mode selection, as described in table 2. the timing diagrams in figures 16 and 17 show the output timing and data alignment in div1, div2, and div4 modes, respectively. the phase relationship between the sampling clock at the clk+/clk- inputs and the data-ready clock at the dready+/dready- outputs will be random at device power-up. as with all divide-by-two circuits, two possi- ble phase relationships exist between these clocks. the difference between the phases is simply the inver- sion of the div2-dready clock. the timing diagram in figure 16 shows this relationship. reset all MAX108 devices to a known dready phase after initial power-up for applications such as interleav- ing, where two or more MAX108 devices are used to achieve higher effective sampling rates. this synchro- nization is necessary to set the order of output samples between the devices. resetting the converters accom- plishes this synchronization. the reset signal is used to force the internal counter in the demux clock-generator block to a known phase state. MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 21 table 6. demux operating and reset control signals 50% clk+ clk- dready + dready - "phase 1" "phase 2" 20% 20% 50% 80% 80% t pd1 dready- dready+ t rdready t fdready figure 16. clk and dready timing in demuxed div2 mode showing two possible dready phases clk+ clk- dready + dready - auxiliary port data primary port data t pwh t pwl t pd1 t pd2 figure 17. output timing for all modes (div1, div2, div4) function signal name rstout+, rstout- reset outputs for resetting additional external demux devices. differential pecl outputs rstin+, rstin- demux reset input signals. resets the internal demux when asserted. differential pecl inputs dready+, dready- data-ready pecl output. output data changes on the rising edge of dready+. differential pecl outputs type clk+, clk- master adc timing signal. the adc samples on the rising edge of clk+. sampling clock inputs
MAX108 reset output finally, the reset signal is presented in differential pecl format to the last block of the reset signal path. rstout+/rstout- output the time-aligned reset sig- nal, used for resetting additional external demuxes in applications that need further output data-rate reduc- tion. many demux devices require their reset signal to be asserted for several clock cycles while they are clocked. to accomplish this, the MAX108 dready clock will continue to toggle while rstout is asserted. when a single MAX108 device is used, no synchroniz- ing reset is required because the order of the samples in the output ports is unchanged, regardless of the phase of the dready clock. in div2 mode, the data in the auxiliary port is delayed by 8.5 clock cycles, while the data in the primary port is delayed by 7.5 clock cycles. the older data is always in the auxiliary port, regardless of the phase of the dready clock. the reset output signal, rstout, is delayed by one fewer clock cycles (6.5 clock cycles) than the primary port. the reduced latency of rstout serves to mark the start of synchronized data in the primary and auxil- iary ports. when the rstout signal returns to a zero, the dready clock phase is reset. since there are two possible phases of the dready clock with respect to the input clock, there are two pos- sible timing diagrams to consider. the first timing dia- gram (figure 18) shows the rstout timing and data alignment of the auxiliary and primary output ports when the dready clock phase is already reset. for this example, the rstin pulse is two clock cycles long. under this condition, the dready clock continues uninterrupted, as does the data stream in the auxiliary and primary ports. the second timing diagram (figure 19) shows the results when the dready phase is opposite from the reset phase. in this case, the dready clock swallows a clock cycle of the sample clock, resynchronizing to the reset phase. note that the data stream in the auxil- iary and primary ports has reversed. before reset was 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 22 ______________________________________________________________________________________ figure 18. reset output timing in demuxed div2 mode (dready aligned) note: the latency to the reset output is 6.5 clock cycles. the latency to the primary port is 7.5 clock cycles, and the latency to the auxiliary port is 8.5 clock cycles. all data ports are updated on the rising edge of the dready + clock. clk- clk+ t su t hd n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready dready+ dready- rstin+ rstin- rstout+ rstout- reset input n+1 n-1 n+3 auxiliary data port primary data port n n+2 n+4 reset out data port
asserted, the auxiliary port contained even samples while the primary port contained odd samples. after the rstout is deasserted (which marks the start of the dready clocks reset phase), note that the order of the samples in the ports has been reversed. the auxiliary port also contains an out-of-sequence sample. this is a consequence of the swallowed clock cycle that was needed to resynchronize dready to the reset phase. also note that the older sample data is always in the auxiliary port, regardless of the dready phase. these examples illustrate the combinations that result with a reset input signal of two clock cycles. it is also possible to reset the internal MAX108 demux success- fully with a reset pulse of only one clock cycle, provid- ed that the setup time and hold-time requirements are met with respect to the sample clock. however, this is not recommended when additional external demuxes are used. note that many external demuxes require their reset signals to be asserted while they are clocked, and may require more than one clock cycle of reset. more impor- tantly, if the phase of the dready clock is such that a clock pulse will be swallowed to resynchronize, then no reset output will occur at all. in effect, the rstout signal will be swallowed with the clock pulse. the best method to ensure complete system reset is to assert rstin for the appropriate number of dready clock cycles required to complete reset of the external demuxes. die temperature measurement for applications that require monitoring of the die tem- perature, it is possible to determine the die temperature of the MAX108 under normal operating conditions by observing the currents i const and i ptat , at contacts iconst and iptat. i const and i ptat are two 100a (nominal) currents that are designed to be equal at +27c. these currents are derived from the MAX108s internal precision +2.5v bandgap reference. i const is designed to be temperature independent, while i ptat is directly proportional to the absolute temperature. these currents are derived from pnp current sources refer- enced from v cc i and driven into two series diodes con- nected to gndi. the contacts iconst and iptat may be left open because internal catch diodes prevent sat- uration of the current sources. the simplest method of determining the die temperature is to measure each MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 23 figure 19. reset output timing in demuxed div2 mode (dready realigned) note: dready phase was adjusted to match the reset phase by ?wallowing?one input clock cycle. the auxiliary port contains an out-of-sequence sample as a result of the delay. clk- clk+ t su t hd n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clock pulse ?wallowed out-of-sequence sample clk dready dready+ dready- rstin+ rstin- rstout+ rstout- reset input n-1 n+1 n-2 auxiliary data port primary data port n n+2 n+4 reset out data port
MAX108 current with an ammeter (which shuts off the internal catch diodes) referenced to gndi. the die temperature in c is then calculated by the expression: another method of determining the die temperature uses the operational amplifier circuit shown in figure 20. the circuit produces a voltage that is proportional to the die temperature. a possible application for this signal is speed control for a cooling fan to maintain constant MAX108 die temperature. the circuit operates by converting the i const and i ptat currents to volt- ages v const and v ptat , with appropriate scaling to account for their equal values at +27c. this voltage difference is then amplified by two amplifiers in an instrumentation-amplifier configuration with adjustable gain. the nominal value of the circuit gain is 4.5092v/v. the gain of the instrumentation amplifier is given by the expression: to calibrate the circuit, first connect pins 2 and 3 on ju1 to zero the input of the ptat path. with the MAX108 powered up, adjust potentiometer r3 until the voltage at the v temp output is -2.728v. connecting pins 1 and 2 on ju1 restores normal operation to the circuit after the calibration is complete. the voltage at the v temp node will then be proportional to the actual MAX108 die temperature according to the equation: t die (c) = 100 v temp the overall accuracy of the die temperature measure- ment using the operational-amplifier scaling circuitry is limited mainly by the accuracy and matching of the resistors in the circuit. thermal management depending on the application environment for the esbga-packaged MAX108, the customer may have to apply an external heatsink to the package after board assembly. existing open-tooled heatsinks are available from standard heatsink suppliers (see heatsink manufacturers ). the heatsinks are available with preap- plied adhesive for easy package mounting. a v vv a r r r r v temp const ptat v = - =+ + 1 1 2 2 1 3 t i i die ptat const = ? ? - 300 273 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 24 ______________________________________________________________________________________ figure 20. die temperature acquisition circuit with the max479 v const v temp r1 7.5k r2 15k r2 15k 3.32k 5k r1 7.5k 6.65k 6.65k 6.05k 12.1k 12.1k 1 2 3 ju1 10-turn i ptat v ptat i const 1/4 max479 1/4 max479 1/4 max479 1/4 max479
thermal performance the MAX108 has been modeled to determine the ther- mal resistance from junction to ambient. table 7 lists the adcs thermal performance parameters: ambient temperature: t a = +70c heatsink dimensions: 25mm x 25mm x 10mm pc board size and layout: 4 in. x 4 in. 2 signal layers 2 power layers heatsink manufacturers aavid engineering and ierc provide open-tooled, low- profile heatsinks, fitting the 25mm x 25mm esbga package. aavid engineering, inc. phone: 714-556-2665 heatsink catalog no.: 335224b00032 heatsink dimensions: 25mm x 25mm x 10mm international electronic research corporation (ierc) phone: 818-842-7277 heatsink catalog no.: bdn09-3cb/a01 heatsink dimensions: 23.1mm x 23.1mm x 9mm bypassing/layout/power supply grounding and power-supply decoupling strongly influ- ence the MAX108s performance. at a 1.5ghz clock frequency and 8-bit resolution, unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections and adversely influence the dynamic performance of the adc. therefore, closely follow the grounding and power-sup- ply decoupling guidelines (figure 22). maxim strongly recommends using a multilayer printed circuit board (pcb) with separate ground and power- supply planes. since the MAX108 has separate analog and digital ground connections (gnda, gndi, gndr, and gndd, respectively), the pcb should feature sep- arate analog and digital ground sections connected at only one point (star ground at the power supply). digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. high- speed signals, including clocks, analog inputs, and digital outputs, should be routed on 50 microstrip lines, such as those employed on the MAX108 evalua- tion kit. the MAX108 has separate analog and digital power- supply inputs: v ee (-5v analog and substrate supply) and v cc i (+5v) to power the t/h amplifier, clock distri- bution, bandgap reference, and reference amplifier; v cc a (+5v) to supply the adcs comparator array; v cc o (+3v to v cc d) to establish power for all pecl- based circuit sections; and v cc d (+5v) to supply all logic circuits of the data converter. the MAX108 v ee supply contacts must not be left open while the part is being powered up. to avoid this condition, add a high-speed schottky diode (such as a motorola 1n5817) between v ee and gndi. this diode prevents the device substrate from forward biasing, which could cause latchup. MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 25 figure 21. MAX108 thermal performance 6 8 10 12 14 16 18 0 200 100 300 400 500 600 700 800 thermal resistance vs. airflow airflow (linear ft./min.) q ja (?/w) without heatsink with heatsink table 7. thermal performance for MAX108 with or without heatsink 16.5 12.5 airflow (linear ft/min) 0 MAX108 q ja (c/w) 14.3 9.4 200 13 8.3 400 12.5 7.4 800 without heatsink with heatsink
MAX108 all supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the pcb. for best performance, bypass all power supplies to the appropriate ground with a 10f tantalum capacitor to filter power-supply noise, in parallel with a 0.1f capacitor and a high-quality 47pf ceramic chip capaci- tor located very close to the MAX108 device to filter very high-frequency noise. static parameter definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the MAX108 are mea- sured using the best-straight-line fit method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 26 ______________________________________________________________________________________ figure 22. MAX108 bypassing and grounding 10 m f gndd v cc d gnda v cc a gndi v cc i gndi 1n5817 v ee v cc a = +4.75v to +5.25v v cc d = +4.75v to +5.25v v cc i = +4.75v to +5.25v v cc o = +3.0v to v cc d v ee = -4.75v to -5.25v note: locate all 47pf capacitors as close as possible to the MAX108 device. gndd v cc o 10nf 10nf 47pf 47pf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 47pf 47pf
bit error rates errors resulting from metastable states may occur when the analog input voltage (at the time the sample is taken) falls close to the decision point of any one of the input comparators. here, the magnitude of the error depends on the location of the comparator in the com- parator network. if it is the comparator for the msb, the error will reach full scale. the MAX108s unique encod- ing scheme solves this problem by limiting the magni- tude of these errors to 1lsb. dynamic parameter definitions signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adcs reso- lution (n bits): snr (max) = (6.02 n + 1.76)db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. effective number of bits enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantization noise only. enob is calculated from a curve fit referenced to the theoreti- cal full-scale range. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is calculated from the enob as follows: sinad = (6.02 enob) + 1.76 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio, expressed in decibels, of the rms amplitude of the fun- damental (maximum signal component) to the rms value of the next largest spurious component, exclud- ing dc offset. intermodulation distortion the two-tone intermodulation distortion (imd) is the ratio, expressed in decibels, of either input tone to the worst 3rd-order (or higher) intermodulation products. the input tone levels are at -7db full scale. thd 20 log v v v v / v 2 2 3 2 4 2 5 2 1 =+++ ? ? ? ? ? ? ? MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 27 chip information transistor count: 20,486 substrate connected to v ee
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 28 ______________________________________________________________________________________ typical operating circuit MAX108 z 0 = 50 w 50 w all pecl outputs must be terminated like this. v cc o - 2v p7+/p7- p5+/p5- p3+/p3- p1+/p1- a7+/a7- a5+/a5- a3+/a3- to memory or digital signal processor a1+/a1- 2 2 p6+/p6- 2 p4+/p4- 2 p2+/p2- 2 or+/or- v ee v cc av cc iv cc dv cc o auxen1 auxen2 -5v analog divselect demuxen +5v digital vosadj vin- clk+ clk- clkcom rstin+ rstin- +5v analog +5v digital +3.3v digital dready+/dready- rstout+/rstout- primary pecl outputs p0+/p0- 2 a6+/a6- 2 a4+/a4- 2 a2+/a2- 2 a0+/a0- 2 2 2 2 2 2 2 2 2 2 auxilary pecl outputs gnda gndi gndi gndr gndi gndd refout refin z 0 = 50 w z 0 = 50 w vin+ differential analog input 500mvp-p fs sample clock 1.5ghz +4dbm z 0 = 50 w 50 w
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 29 top view +5v track/hold analog +5v comparator analog +5v logic digital -5v track/hold analog +3.3v pecl supply t/h ground comparator ground logic ground vcci vcca vccd vee vcco gndi gnda gndd MAX108 MAX108 192 ball esbga printed circuit board (pcb) land pattern 192-contact esbga pcb land pattern
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier 30 ______________________________________________________________________________________ package information super bga.eps
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier ______________________________________________________________________________________ 31 package information (continued)
MAX108 5v, 1.5gsps, 8-bit adc with on-chip 2.2ghz track/hold amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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